This invention relates to complementary-metal-oxide-semiconductor (CMOS) integrated circuits and, more particularly, to a CMOS integrated circuit configuration in which the coupling of noise signals to certain nodes thereof is substantially reduced.
Integrated circuits such as switched capacitor filters or analog-to-digital converters having high-impedance summing node points are particularly susceptible to noise signals. If these signals exceed specified levels, the operating characteristics of the circuit will be seriously degraded and the circuit will not be acceptable for inclusion in a high-performance signal processing system such as a single-chip pulse-code-modulation (PCM) coder-decoder (CODEC) with filters.
In practice, various noise signals are parasitically coupled to the aforespecified node points from off-chip supplies and distribution buses connected to the substrate and to so-called tubs formed in the substrate of the CMOS integrated circuit chip. The off-chip supplies can, for example, also be corrupted by noise from certain circuitry (for example digital circuits) on the chip. Accordingly, considerable efforts have been directed by circuit designers at trying to devise techniques for improving the performance characteristics of the chip by reducing the coupling of such noise signals to the node points. Heretofore, however, no simple, economical and effective way of achieving a satisfactory reduction of parasitically coupled power supply noise signals to the indicated node points of a CMOS chip has been devised.